Message-based communication is used in some software systems. Such software systems often use shared memory to pass messages. In contrast, processors generally access hardware via a low-speed control/status register (CSR) bus, such as by using an AHB, AMBA, AXI, or PIF (Peripheral InterFace) bus in a master mode. The CSR busses tend to have relatively low bandwidth, particularly for reads by the processor, which tend to be single-threaded.
Embedded controllers, such as a multi-processor solid-state drive (SSD)/non-volatile memory controller, need both fast inter-processor communication and fast control of hardware assists, such as direct memory access (DMA) engines or look-up engines. A conventional approach is to build hardware communication into attached memories of the processor, such as a tightly-coupled data memory that the processor can access via load/store, and the peripherals can access via the ABB, AMBA, AXI, or PIF bus in a slave mode. The conventional approach, however, single-threads access by the peripherals to the shared memory, and also imposes a relatively high management overhead on the processor.
It would be desirable to implement unified message-based communications.